1. Field of the Invention
The present invention relates to a semiconductor package and methods of fabricating the same, and more particularly, to a semiconductor package having a power device and methods of fabricating the same.
2. Description of the Related Art
In general, a semiconductor package is fabricated by sealing one or more semiconductor chips with a sealing material, such as an epoxy mold compound (EMC), so as to protect the inside thereof, and then the one or more semiconductor chips are mounted on a printed circuit board (PCB).
However, as electronic appliances have been developed to operate at high speeds, to have large capacities, and have been miniaturized, power devices applied to automobiles, industrial equipment, and electric home appliances also need to be manufactured at low cost and become smaller and lighter. At the same time, power devices need to operate with high reliability. Therefore, use of a multi-chip power module package in which a plurality of semiconductor chips are mounted on one semiconductor package is popular.
For example, U.S. Pat. No. 5,703,399 assigned to Mitsubishi discloses a power semiconductor module package. The semiconductor package is constructed in such a manner that a plurality of semiconductor chips, such as a power circuit and a control circuit, are mounted on a lead frame. In the semiconductor package, a sealing material having high thermal conductivity is applied to the bottom of the lead frame, and a heat sink formed of copper is located slightly separated from the lead frame under the lead frame. Accordingly, heat generated by a power circuit chip can be effectively dissipated to the outside.
However, the power semiconductor module package has the following disadvantages. First, the sealing material is filled between a rear surface of the lead frame and the copper heat sink in order to maintain electrical insulating characteristics therebetween. However, while the thermal conductivity of the sealing material is high, it is still less than the thermal conductivity of the lead frame and the copper heat sink, for example, which affects the operating temperature of the semiconductor chips.
Second, since different types of sealing materials are applied on one power semiconductor module package, the process for manufacturing the power semiconductor module package is complicated.
Third, if a plurality of semiconductor chips are mounted on a lead frame, it is difficult to maintain electrical insulation between the semiconductor chips on the lead frame. In particular, this problem becomes serious in the case of a high voltage power device.
In order to solve these problems, a method of fabricating a power semiconductor module package using an insulated substrate, such as a direct bonding copper (DBC) substrate or an insulated metal substrate (IMS), has been introduced.
The DBC substrate is constructed in such a manner that a copper layer is attached to both surfaces of a ceramic layer having high electrical insulating characteristics, and high thermal dissipation characteristics. However, manufacturing costs of the DBC substrate are high.
The IMS is fabricated by forming a polymer insulation layer on an aluminum substrate and then forming a copper layer on the polymer insulation layer according to a designed pattern. Thus, the manufacturing costs of the IMS are lower than those of the DBC substrate. However, the IMS has poor thermal and electrical insulating characteristics.
Accordingly, there is a need to develop a semiconductor package using an insulated structure having low thermal resistivity and high electric resistivity, rather than an insulating substrate, such as the DBC substrate or the IMS, and a method of fabricating the same.